August 16, 2022

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x86 & Arm Rival, RISC-V Architecture Ships 10 Billion Cores

x86 & Arm Rival, RISC-V ships with 10 billion core architecture

Calista Redmond, CEO of RISC-V International, announced at Embedded World that there are currently ten billion RISC-V centers on the market.

The ARM RISC-V architecture has shipped 10 billion cores, said to be more prominent than the x86 & Arm architecture of the future.

RISC-V, pronounced “The Fifth Risk”, is an Open Standard Instruction Set (ISA) architecture that is provided under open source licenses and is free to use. The basic set of instructions contains fixed-length 32-bit naturally aligned instructions, and ISA supports variable-length extensions, meaning that each instruction can be of any numerical length within 16-bit parcels. The instruction set comes in 32-bit and 64-bit address space flavors and is built for a wide variety of uses. The various subgroups support everything from mini-embedded systems to PCs to processor-bound supercomputers to warehouse-level rack-mounted parallel PCs.

Calista Redmond said open standards are key.

Linux does this for software, and we do it for hardware. We estimate that there are 10 billion RISC-V centers on the market.

But the path to ten billion was no quick task. It is reported that seventeen years of trial and error for the ARM architecture took the major milestone to be achieved in 2008. On the other hand, RISC-V took only twelve years to complete ten billion. Redmond predicts that the number of RISC-V processor cores is expected to reach 80 billion by 2025.

Source: Embedded World 2022.

This news included announcing the approval of the four new specifications and extensions as of this year. The Four new specifications be:

  • RISC-V specifications for SBI engineers for the firmware layer between the hardware platform and the operating system kernel using a binary application interface in supervisor mode (S-mode or VS-mode). This abstraction enables cross-platform services across all RISC-V OS implementations. Several RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so certification of the specification will ensure a standard approach is taken across the entire RISC-V ecosystem, ensuring compatibility. The development and validation of this specification was led by Atesh Batra of Refus, with work conducted by the platform’s horizontal steering committee.
  • RISC-V UEFI protocols bring current UEFI standards to RISC-V platforms. The development and validation of this specification was led by Sunil VL, Ventana Micro and Philipp Tomsich, VRULL GmbH, with work conducted in the Premium Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient processor tracing method that uses branch tracing, ideal for debugging any type of application from small embedded designs to ultra-powerful computers. The E-Trace of the RISC-V documentation defines the signals between the RISC-V core and the encoder (or the input port), a compressed branch tracing algorithm, and a packet format for encapsulating the compressed branch trace information. Gajinder Panesar of Picocom and RISC-V’s E-Trace Task Group led the development and validation of this specification.
  • RISC-V Zmmul Multiply allows only low-cost implementations that require multiplication but not division and are part of the RISC-V non-premium specification. Allen Baum led the development and validation of this extension, with work performed on the ISA Unlucky Committee.
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news sources: IT HomeAnd the RISV.org